2025, Vol. 6, Issue 2, Part A

With the continuous advancement of radio frequency (RF) communication systems, ever increasing demands are placed on circuit networks to operate at both low power and high frequency. This article focuses on the optimisation of linear circuit networks for low power and high frequency applications. The background arises from the persistent trend of system miniaturisation, higher integration densities and the push toward mobile and battery driven devices, which impart ever stricter constraints on power consumption while pushing circuit topologies into the gigahertz regime. Previous work in low power VLSI and high frequency power electronics has shown that design trade offs between switching losses, parasitic effects and signal integrity are critical [1-3]. In the domain of RF and linear analog circuits the challenge is compounded by the need for linearity, wide bandwidth, and minimal distortion even as switching frequencies rise and supply voltages shrink [4, 5]. The problem statement centres on the design of linear circuit networks that can sustain high frequency operation without incurring prohibitive power losses or sacrificing linearity and stability. Specifically, how can component selection, topology refinement and parasitic mitigation be co optimised to deliver networks suitable for low power high frequency applications?

The objectives of the article are three fold:

1.To characterise the principal limiting factors in linear network design at high frequencies and low power;

2.To propose optimisation strategies that address those limiting factors—such as minimising parasitic capacitances, optimising device sizing, and tailoring impedance matching; and

3.To validate the proposed strategies via analytical or simulation based evaluation in representative linear networks.

Accordingly, the hypothesis is that by systematically modelling parasitic elements, selecting topology and device sizing for minimal loss, and implementing matching networks optimised for high frequency operation, linear circuit networks can achieve significant reductions in power consumption while maintaining target high frequency performance. The expectation is that such integrated optimisation will outperform ad hoc design practices by enabling operation at higher frequency (e.g., hundreds of MHz to several GHz) with lower quiescent and dynamic power usage, improved linearity and bandwidth.