2025, Vol. 6, Issue 1, Part A
Designing an area efficient dynamic register file array through custom cell design optimization
Author(s): Manoj Kumar Paramasivam and Anima Sahu
Abstract: Register file arrays are an integral part of ASIC design and the efficiency of these register file arrays is important to achieve the energy delay product and area design targets. This paper explains an area-efficient design of a 16x16 dynamic register file array with a nominal energy-delay product. We explore circuit-level optimizations, and layout strategies to achieve an efficient design. The proposed register file utilizes dynamic memory elements to enhance density while maintaining speed and reliability.
DOI: 10.22271/27084531.2025.v6.i1a.82
Pages: 22-26 | Views: 55 | Downloads: 20
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How to cite this article:
Manoj Kumar Paramasivam, Anima Sahu. Designing an area efficient dynamic register file array through custom cell design optimization. Int J Res Circuits Devices Syst 2025;6(1):22-26. DOI: 10.22271/27084531.2025.v6.i1a.82
